8086 Micro-Processors and Assembly Programming Forth Stage المعالجات الميكروية والبرمجة بلغة التجميع استاذة الماده: م.د ستار حبيب منعثر الخفاجي

Transcription

1 جامعة ذي قار كلية الهندسة قسم الهندسة الكهربائية وااللكترونية 8086 Micro-Processors and Assembly Programming Forth Stage المعالجات الميكروية والبرمجة بلغة التجميع استاذة الماده: م.د ستار حبيب منعثر الخفاجي

2 2 References The 8086 Microprocessors Architecture, software and Interfacing techniques By: Walter A. Triebel The 8086/8088 MPU, Architecture, programming and interfacing BY: Barry B. Brey

3 Microcomputer Architecture 3 A computer system has three main components: a Central Processing Unit (CPU) or processor, a Memory Unit and Input Output Units (devices). In any microcomputer system, the component which actually processes data is entirely contained on a single chip called Microprocessor (MPU). This MPU can be programmed using assembly language. Writing a program in assembly language requires a knowledge of the computer hardware (or Architecture) and the details of its instruction set. The main internal hardware features of a computer are the processor, memory and registers (registers are special processor components for holding address and data). The external hardware features are the computer Input/Output devices such as keyboard, monitor Software consists of the operating system (O.S) and various programs and data files stored on disk. Inside any computer based on a member of the 8086 family, the basic arrangement of the main components is shown in Figure 1.

4 4 CS Microproces IP INT Type 255 Input Device Ex: Ke y board EU Execute instruction BIU Fetch & Decode instruction Memory ROM RAM Backing store disk display Output Ex: Screen 003 FF 003 FE System Bus 003 FD 003 FC Figure 1: Data flow between the main components of an 8086 family computer. Information is sent from one main component to another along the communication channel, which is often called the System Bus. Both programs and data are stored in the memory. The Bus Interface Unit (BIU) within the MPU fetches new instruction or data as necessary. It is also the BIU jobs to interpret or decode instruction and to route results to their proper destination. The MPU Execution Unit carries out any arithmetic which is required, including memory calculation. Microcomputer memories consist of a collection of chips of two kinds Read Only Memory (ROM) and Random Access Memories (RAM).

5 System Bus 5 The components of the computer system must communicate with each other and with the outside world. Although it may be possible to connect each component to the CPU separately as a practical matter this would require too many physical connects. To keep the number of connections manageable, the processor is connected to memory and all peripherals using a bus. A Bus is a bunch of wires, and electrical path on the printed IC to which every thing in the system is connected. There are three types of Bus: 1- Address Buss (AB): the width of AB determines the amount of physical memory addressable by the processor. 2- Data Bus (DB): the width of DB indicates the size of the data transferred between the processor and memory or I/O device. 3- Control Bus (CB): consists of a set of control signals, typical control signals includes memory read, memory write, I/O read, I/O write, interrupt acknowledge, bus request. These control signals indicates the type of action taking place on the system bus.

6 Personal Computer (PC) Components 6 The main component of the PC is its System Board (or mother board). It contains the processor, co-processor, main memory, connectors, and expansion slots for optional cards. The slots and connectors provide access to such components as ROM, RAM, hard disk, CD-ROM drive, additional memory, video unit, keyboard, mouse, parallel and serial device, sound adapter and cache memory (the processor use high speed cache memory to decrease its need to access the slower main memory). A bus with wires attached to the system board connect the components. It transfers data between the processor, memory and external devices. A. The processor The CPU or processor acts as the controller of all actions or services provided by the system. The operations of a CPU can be reduced to three basic steps: fetch, decode, and execute. Each step includes intermediate steps, some of which are: 1- Fetch the next instruction: - Place it in a holding area called a queue. - Decode the instruction. 2- Decode the instruction - Perform address translation. - Fetch operand from memory. 3- Execute the instruction. - Perform the required calculation.

7 7 - Store results in memory or register. - Set status flag attached to the CPU. Figure 2 shows a block diagram of a simple imaginary CPU. The CPU is divided into two general parts. Arithmetic Logic Unit (ALU) and Control Unit (CU). - The ALU carry Arithmetic, logical, and shifting operations. - The CU fetches data and instruction, and decodes addresses for the ALU. Data Bus Data Register Address Register CU ALU Memory Address Bus Figure 2: A block diagram of a simple CPU. B. Memory

8 8 The memory of a computer system consist of tiny electronic switches, with each switch set in one of two states: open or close. It is however more convenient to think of these states as 0 and 1. Thus each switch can represent a binary digit or bit, as it is known, the memory unit consists of millions of such bits, bits are organized into groups of eight bits called byte. Memory can be viewed as consisting of an ordered sequence of bytes. Each byte in this memory can be identified by its sequence number starting with 0, as shown in Figure 3. This is referred to as memory address of the byte. Such memory is called byte addressable memory can address up to 1 MB (2 20 bytes) of main memory this magic number comes from the fact that the address bud of the 8086 has 20 address lines. This number is referred to as the Memory Address Space (MAS). The memory address space of a system is determined by the address bus width of the CPU used in the system. The actual memory in a system is always less than or equal to the MAS. Address Decimal in Address in Hex...

9 FFFFF FFFFE Figure 3: Logical view of the system memory Two basic memory operations The memory unit supports two fundamental operations: Read and Write. The read operation read a previously stored data and the write operation stores a value in memory. See Figure 4 Address Read Write Memory Unit Data Figure 4: Block diagram of system memory

10 10 Steps in a typical read cycle: 1- Place the address of the location to be read on the address bus. 2- Activate the memory read control signal on the control bus. 3- Wait for the memory to retrieve the data from the address memory location. 4- Read the data from the data bus. 5- Drop the memory read control signal to terminate the read cycle. Steps in a typical write cycle: 1- Place the address of the location to be written on the address bus. 2- Place the data to be written on the data bus. 3- Activate the memory write control signal on the control bus. 4- Wait for the memory to store the data at the address location.. 5- Drop the memory write control signal to terminate the write cycle. Addresses: group of bits which are arranged sequentially in memory, to enable direct access, a number called address is associated with each group. Addresses start at 0 and increase for successive groups. The term location refers to a group of bits with a unique address. Table 1 represents Bit, Byte, and Larger units. Table1: Bit, Byte, and Larger units.

11 Name Bit 0 or 1 Byte Number of Byte is a group of bits used to represent a character, typically 8-bit. 11 Word Double Word Quadword Paragraph 2-bytes (16-bit) data item 4-byte (32-bits) 8-Bytes (64-bit) 16-bytes (128-bit) KiloByte (KB) the number 2 10 = 1024 = 1K for KiloByte, (thus 640K = 640 * 1024 = bytes) Types of memory The memory unit can be implemented using a variety of memory chips- different speeds, different manufacturing technology, and different sizes. The two basic types are RAM and ROM. 1- Read Only Memories (ROM): ROMs allow only read operation to be performed. This memory is non-volatile. Most ROMs are programmed and cannot be altered. This type of ROM is cheaper to manufacture than other types of ROM. The program that controls the standard I/O functions (called BIOS) is kept in ROM, configuration software.

12 12 Other types of ROM include: - Programmable ROM (PROM). - Erasable PROM (EPROM) is read only memory that can be reprogrammed using special equipment. - EAPROM, Electrically Alterable Programmable ROM is a Read Only Memory that is electrically reprogrammable. 2- Read/Write Memory Read/Write memory is commonly referred to as Random Access Memory (RAM), it is divided into static and dynamic. Static RAM (SRAM): used for implementing CPU registers and cache memories. Dynamic RAM (DRAM), the bulk of main memory in a typical computer system consists of dynamic ram. Dynamic RAM: main memory, or RAM is where program, data are kept when a program is running. It must be refreshed with in less than a millisecond or losses its contents. Static RAM, used for special high speed memory called cache memory which greatly improves system performance. Static RAM keeps its value without having to be refreshed. C. INPUT/OUTPUT Input/Output (I/O) devices provide the means by which the computer system can interact with the outside world. Computers

13 13 use I/O devices (also called peripheral devices) for two major purposes: 1- To communicate with the outside world and, 2- Store data. Devices that are used to communicate like, printer, keyboard, modem, Devices that are used to store data like disk drive. I/O devices are connected to the system bus through I/O controller (interface) which acts as interface between the system bus and I/O devices. There are two main reasons for using I/O controllers 1- I/O devices exhibit different characteristics and if these devices are connected directly, the CPU would have to understand and respond appropriately to each I/O device. This would cause the CPU to spend a lot of time interacting with I/O devices and spend less time executing user programs. 2- The amount of electrical power used to send signals on the system bus is very low. This means that the cable connecting the I/O device has to be very short (a few centimeters at most). I/O controllers typically contain driver hardware to send current over long cable that connects I/O devices. See Figure5.

14 14 Address Data DataBus ControlBus Status Command I/O Device I/O Controller Figure5: Block diagram of a generic I/O device interface. Evolution of Intel Microprocessor The principle way in which MPU & microcomputer are categorized in term of the maximum number of binary bit in the data they process that is, their word length. Processor vary in their speed, capacity of memory, register and data bus, below are a brief description of various Intel processor in Table and 8086 functionally identical but 8088 lower performance, run all 8088 and 8086 software, but have 10 new instructions in function is identical to but lower performance run all 8086, program, but has extra instruction, more powerful than has various operation mode, which allow it to act as chip or multiple 8086 chip, as well as a set of instruction capable of 32 bit operations such as arithmetic.

15 Table 2: Different Microprocessor features descriptions 15 Microprocessor Name Width of (DB) Features Descriptions Width of (AB) bit 20 bit 6 Byte bit 20 bit 4 Byte bit 20 bit 6 Byte bit 20 bit 4 Byte bit 24 bit 6 Byte bit 32 bit 6 Byte Instruction queue length Execution Unit and Bus Interface Unit In the Figure 6, the processor is partitioned into two logical units: an Execution Unit (EU) and Bus Interface Unit (BIU). The role of the EU is to execute instruction, whereas the BIU delivers instruction and data to EU. The EU contains ALU, CU and number of registers. This feature enables the EU to execute instructions and perform arithmetic and logical operations. The most important function of BIU is to manage the bus control unit, segment registers instruction queue. The BIU controls the busses that transfer data to the EU, to memory, and to external input/output devices, whereas the segment registers control the memory addressing.

16 16 AH BH CH DH SP BP SI AL BL CH DL Program Control CS DS SS ES DI Bus Control Unit ALU CU Flag Instruction Queue IP N Execution Unit Bus Interface Unit Figure 6: Execution unit and Bus interface unit. Another function of the BIU is to provide access to instructions, because the instructions for a program that is executing are kept in

17 17 memory, the BIU must access instruction from memory and place them in an instruction queue, which varies in size depending on the processor. This feature enables the BIU to look ahead and prefetch instructions, so that there is always a queue of instructions ready to execute. The EU and BIU work in parallel, with the BIU keeping one step ahead. The EU notifies the BIU when it needs access to data in memory or I/O devices. Also the EU request machine code instructions from the BIU instruction queue. The top instruction is the currently executable one, and while the EU is occupied executing an instruction, the BIU fetch another instruction from memory. This fetching overlaps with execution and speeds up processing. Addressing Data in Memory Depending on the model, the processor can access one or more bytes of memory at a time. Consider the Hexa value (0529 H ) which requires two bytes or one word of memory. It consist of high order (most significant) byte 05 and a low order (least significant) byte 29. The processor store the data in memory in reverse byte sequence i.e. the low order byte in the low memory address and the high order byte in the high memory address. For example, the processor transfer the value 0529 H from a register into memory address 04A26 H and 04A27 H like this:

18 18 Register FFFFF A28 Most Significant Byte A27 Least Significant Byte A Memory The processor expects numeric data in memory to be in reverse byte sequence and processes the data accordingly, again reverses the bytes, restoring them to correctly in the register as hexa 0529 H. When programming in assembly language, you have to distinguish between the address of a memory location and its contents. In the above example the content of address 04A26 H is 29, and the content of address 04A27 H is 05. There are two types of addressing schemes: 1. An Absolute Address, such as 04A26 H, is a 20 bit value that directly references a specific location. 2. A Segment Offset Address, combines the starting address of a segment with an offset value.

19 Segments and Addressing 19 Segments are special area defined in a program for containing the code, the data, and the stack. Segment Offset within a program, all memory locations within a segment are relative to the segment starting address. The distance in bytes from the segment address to another location within the segment is expressed as an offset (or displacement). To reference any memory location in a segment, the processor combine the segment address in a segment register with the offset value of that location, that is, its distance in byte from the start of the segment. Specifying addresses To represent a segment address and its relative offset we use the notation: Segment: offset Thus 020A:1BCD denotes offset 1BCD H from segment 020A H. The actual address it refers to is obtained in the following way: 1- Add zero to the right hand side of the segment address. 2- Add to this the offset. Hence the actual address referred to by 020A:1BCD is 03C6D.

20 20 FFFFF Memory= 1 MB Only 64 KB can be used by IP since it is 16-bit register FF Address Bus in the 8086 is 20 bits wide (20 lines) i.e. the processor can access memory of size 2 20 or bytes (1MB). Instruction Pointer = 16 bit register which means the processor can only address (65535) bytes of memory. But we need to write instructions in any of the 1MB of memory. This can be solved by using memory segmentation., where each segment register is 16-bit (this 16-bit is the high 16-bit of Address Bus (A 4 A 19 )) i.e. each of the segment registers represent the actual address after shifting the address 4-bit to get 20 bits. Registers Registers are 8, 16, or 32-bit high speed storage locations directly inside the CPU, designed to be accessed at much higher speed than conventional memory.

21 21 General Purpose Index Reg. AX AH AL BP BX BH BL SP CX CH CL SI DX DH DL DI Status & Control Flag IP Segment Reg. CS SS DS ES Figure 7: Intel 16-bit registers The CPU has an internal data bus that is generally twice as wide as its external data bus. Data Registers: The general purpose registers, are used for arithmetic and data movement. Each register can be addressed as either 16-bit or 8 bit value. Example, AX register is a 16-bit register, its upper 8-bit is called AH, and its lower 8-bit is called

22 22 AL. Bit 0 in AL corresponds to bit 0 in AX and bit 0 in AH corresponds to bit 8 in AX. See Figure AX AH AL Figure 8: AX register Instructions can address either 16-bit data register as AX, BX, CX, and DX or 8-bit register as AL, AH, BL, BH, CL, CH, Dl, and DH. If we move 126F H to AX then AL would immediately 6F H and AH = 12 H. * Each general purpose register has special attributes: 1- AX (Accumulator): AX is the accumulator register because it is favored by the CPU for arithmetic operations. Other operations are also slightly more efficient when performed using AX. 2- BX (Base): the BX register can hold the address of a procedure or variable. Three other registers with this ability are SI, DI and BP. The BX register can also perform arithmetic and data movement.

23 23 3- CX (Counter): the CX register acts as a counter for repeating or looping instructions. These instructions automatically repeat and decrement CX. 4- DX (Data): the DX register has a special role in multiply and divide operation. When multiplying for example DX hold the high 16 bit of the product. * Segment Registers: the CPU contain four segment registers, used as base location for program instruction, and for the stack. 1- CS (Code Segment): The code segment register holds the base location of all executable instructions (code) in a program. 2- DS (Data Segment): the data segment register is the default base location for variables. The CPU calculates their location using the segment value in DS. 3- SS (Stack Segment): the stack segment register contain the base location of the stack. 4- ES (Extra Segment): The extra segment register is an additional base location for memory variables. * Index registers: index registers contain the offset of data and instructions. The term offset refers to the distance of a variable, label, or instruction from its base segment. The index registers are:

24 24 1- BP (Base Pointer): the BP register contain an assumed offset from the stack segment register, as does the stack pointer. The base pointer register is often used by a subroutine to locate variables that were passed on the stack by a calling program. 2- SP (Stack Pointer): the stack pointer register contain the offset of the top of the stack. The stack pointer and the stack segment register combine to form the complete address of the top of the stack. 3- SI (Source Index): This register takes its name from the string movement instruction, in which the source string is pointed to by the source index register. 4- DI (Destination Index): the DI register acts as the destination for string movement instruction. Status and Control register: 1- IP (Instruction Pointer): The instruction pointer register always contain the offset of the next instruction to be executed within the current code segment. The instruction pointer and the code segment register combine to form the complete address of the next instruction. 2- The Flag Register: is a special register with individual bit positions assigned to show the status of the CPU or the result

25 25 of arithmetic operations. The Figure9 describe the 8086/8088 flags register: X X X X O D I T S Z X A X P X C O= Over Flow S= sign D= Direction Z=Zero I= Interrupt A= Auxiliary T= trap P= parity X= Undefined C= carry Figure 9: Flag Register. There two basic types of flags: (control flags and status flags) 1- Control Flags: individual bits can be set in the flag register by the programmer to control the CPU operation, these are - The Direction Flag (DF): affects block data transfer instructions, such as MOVS, CMPS, SCAS. The flag values are 0 = up and 1 = down. - The Interrupt flag (IF): dictates whether or not a system interrupt can occur. Such as keyboard, disk drive, and the system clock timer. A program will sometimes briefly disable the interrupt when performing a critical

26 26 operation that cannot be interrupted. The flag values are 1 = enable, 0 = disable. - The Trap flag (TF): Determine whether or not the CPU is halted after each instruction. When this is set, a debugging program can let a programmer to enter single stepping (trace) through a program one instruction at a time. The flag values are 1 = on, 0 = off. The flag can be set by INT 3 instruction. 2- Status Flags: The status flags reflect the outcomes of arithmetic and logical operations performed by the CPU, these are: - The Carry Flag (CF): is set when the result of an unsigned arithmetic operation is too large to fit into the destination for example, if the sum of 71 and 99 where stored in the 8-bit register AL, the result cause the carry flag to be 1. The flag values = 1 = carry, 0 = no carry. - The Overflow (OF): is set when the result of a signed arithmetic operation is too wide (too many bits) to fit into destination. 1 = overflow, 0 = no overflow. - Sign Flag (SF): is set when the result of an arithmetic of logical operation generates a negative result, 1= negative, 0 = positive. - Zero Flag (ZF): is set when the result of an arithmetic of logical operation generates a result of zero, the flag is used primarily by jump or loop instructions to allow branching to a new location in a program based on the comparison of two values. The flag value = 1 = zero, & 0 = not zero.

27 27 - Auxiliary Flag: is set when an operation causes a carry from bit 3 to bit 4 (or borrow from bit 4 to bit 3) of an operand. The flag value = 1 = carry, 0 = no carry. - Parity Flag: reflect the number of 1 bits in the result of an operation. If there is an even number of bit, the parity is even. If there is an odd number of bits, parity is odd. This flag is used by the OS to verify memory integrity and by communication software to verify the correct transmission of data. Instruction Execution and Addressing An assembly language programmer writhe a program in symbolic code and uses the assembler to translate it into machine code as.exe program. For program execution, the system looks only the machine code into memory. Every instruction consists of at least one operation, such as MOV, ADD. Depending on the operation, an instruction may also have one or more operands that reference the data the operation is to process. The basic steps the processor takes in executing on instruction are: 1. Fetch the next instruction to be executed from memory and place it in the instruction queue.

28 28 2. Decode the instruction calculates addressed that reference memory, deliver data to the Arithmetic Logic Unit, and increment the instruction pointer (IP) register. 3. Execute the instruction, performs the request operation, store the result in a register or memory, and set flags such as zero or carry where required. For an.exe program the CS register provide the address of the beginning of a program code segment, and DS provide the address of the beginning of the data segment. The CS contains instructions that are to be executed, where as the DS contain data that the instruction reference. The IP register indicates the offset address of the current instruction in the CS that is to be executed. An instruction operand indicates on offset address in the DS to be referenced. Consider and example in which the program loader has determined that it is to be load on.exe program into memory beginning at location 05BE0 H. The loader accordingly initialize CS with segment address 05BE[0] H and IP with zero. CS: IP together determine the address of the first instruction to execute 05BE0 H H = 05BE0 H. In this way the first instruction in CS being execution, if the first instruction is two byte long, the processor increment IP by 2, so that, the next instruction to be executed is 05BE0 H H = 05BE2 H. Assume the program continues executing, and IP contain the offset 0023 H. CS: IP now determine the address of the next instruction to execute, as follows: CS address: 05BE0 H

29 IP offset: 0023 H + 29 Instruction address: 05C03 H EX: let's say that MOV instruction beginning at 0FC03 H copies the content of a byte in memory into the AL register. The byte is at offset 0016 H in the DS. Her are the machine code and the symbolic code for this operation. Address Symbolic Code MIC code 0FC03 MOV AL, [0016] A A H Address 0FC03 H contain the first byte. (A0 H ) of the MIC code instruction the. The processor is to access 05C03H 05C04 H. 05C05H

30 .. FFFFFH 30 The second and third byte contains the offset value in reversed byte sequence. In symbolic code, the operand [0016] in square brackets (an index operator) indicates an offset value to distinguish it from the actual storage address 16. Lest say that the program has initialized the DS register with DS address 05D1[0] H. To access the data item, the processor determines its location from the segment address in DS + the offset (0016 H ) in the instruction. Operand become DS contain 0FD1[0] H, the actual location of the reference data item is DS: Offset: Address of data item: 05D10 H 0016 H 05D26 H + Assume the address 05D26 H contain 4A H, the processor now extract the 4A H at address 05D26 H and copy it into AL register. An instruction may also access more than one byte at a time EX: Suppose an instruction is to store the content of the AX register (0248 H ) in two adjacent byte in the DS beginning at offset 0016 H. The symbolic code MOV [0016], AX

31 31 The processor stores the two byte in memory in revered byte sequence as Content of AX: in DS: Offset Another instruction, MOV AX, [0016], subsequently could retrieve these byte by copy them from memory back into AX. The operation reverses (and corrects) the byte in AX as: Number of Operands Operands specify the value an instruction is to operate on, and where the result is to be stored. Instruction sets are classified by the number of operands used. An instruction may have no, one, two, or three operands. 1. three-operand instruction: In instruction that have three operands, one of the operand specifies the destination as an address where the result is to be saved. The other two operands specify the source either as addresses of memory location or constants. EX: A=B+C

32 32 EX: ADD destination, source1, source2 ADD A,B,C Y=(X+D)* (N+1) ADD T 1, X, D ADD T 2, N, 1 Mul Y, T 1, T 2 2. Two operand instruction In this type both operands specify sources. The first operand also specifies the destination address after the result is to be saved. The first operand must be an address in memory, but the second may be an address or a constant. ADD destination, source EX: A=B+C EX: Y=(X+D)* (N+1) ADD Y, 1 MOV A, B ADD A, C MOV T 1, X ADD T 1, D MOV Y, N MUL Y, T 1 3. One Operand instruction

33 33 Some computer have only one general purpose register, usually called on Acc. It is implied as one of the source operands and the destination operand in memory instruction the other source operand is specified in the instruction as location in memory. ADD source LDA source; copy value from memory to ACC. STA destination; copy value from Acc into memory. EX: A=B+C EX: Y=(X+D)* (N+1) LDA B LDA X ADD C ADD D STA A STA T 1 LDA N ADD 1 MUL T 1 STA Y 4. Zero Operand instruction Some computers have arithmetic instruction in which all operands are implied, these zero operand instruction use a stack, a stack is a list structure in which all insertion and deletion occur at one end, the element on a stack may be removed only in the reverse of the order in which they were entered. The process of inserting an item is called Pushing, removing an item is called Popping. Computers that use Zero operand instruction for arithmetic operations also use one operand PUSH and POP instruction to copy value between memory and the stack.

34 34 PUSH source; Push the value of the memory operand onto the Top of the stack. POP destination; POP value from the Top of the stack and copy it into the memory operand. EX: A=B+C EX: Y=(X+D)* (N+1) PUSH B PUSH C ADD; POP A Pop the two value of the stack, add 1 them, and then ADD push the sum back PUSH X PUSH D ADD PUSH N PUSH MUL into the stack POP Y

35 35 Assembly Language Instruction Assembly language instructions are provided to describe each of the basic operations that can be performed by a microprocessor. They are written using alphanumeric symbols instead of the 0s and 1s of the microprocessor's machine code. Program written in assembly language are called source code. An assembly language description of this instruction is ADD AX, BX In tins example, the contents of BX and AX are added together and their sum is put in AX. Therefore, BX is considered to be the source operand and AX the destination operand. Here is another example of an assembly language statement: LOOP: MOV AX, BX ; COPY BX INTO AX This instruction statement starts with the word LOOP. It is an address identifier for the instruction MOV AX, BX. This type of identifier is called a label or tag. The instruction is followed by "COPY BX INTO AX." This part of the statement is called a comment. Thus a general format for writing and assembly language statement is: LABEL: INSTRUCTION ; COMMENT

36 36 The 8086 Addressing Mode When the 8086 executes an instruction, it performs the specified function on data. Thee data are called its operands and may be part of the instruction reside in one of the internal registers of the 8086, stored at an address in memory, or held at an I/O port. To access these different types of operands, the 8086 is provided with various addressing modes: 1. Register Addressing Mode With the register addressing mode, the operand to be accessed is specified as residing in an internal register of the 8086, an example of an instruction that uses this addressing mode is MOV AX, BX This stands for move the contents of BX, the source operand, to AX, the destination operand. Both the source and destination operands have been specified as the content of the internal registers of the See Figure 10(a, b). 2. Immediate Addressing Mode If a source operand is part of the instruction instead of the contents of a register or memory location, it represents what is called an immediate operand and is accessed using the immediate addressing mode. Typically, immediate operands represent constant data. Immediate operands can be either a byte or word of data. In the instruction MOV AL, 015H

37 37 The source operand 15 H is an example of a byte-wide immediate source operand. Note that the value of the immediate operand must always be preceded by a zero. See Figure 11(a, b) MPU IP CS DS SS ES Address Memory Content B C3.XX Instruction MOV AX, BX XXXX ABCD AX BX CX DX SP BP SI DI Next Instruction Figure 10(a): Register addressing mode before execution.

38 MPU 0002 IP Address Memory Content Instruction 0100 CS DS B C3 MOV AX, BX ABCD SS ES AX XX Next Instruction ABCD BX CX DX Figure 10(b): Register addressing mode after execution MPU XX SP BP SI DI IP CS DS SS ES AX BX CX DX SP BP SI DI Address Memory Content B0 15.XX XX Instruction MOV AL, 015H Next Instruction Figure 11(a): Immediate addressing mode before execution.

39 MPU 0002 IP Address Memory Content Instruction 0100 CS DS B0 15 MOV AL, 015H 15 SS ES AX BX XX Next Instruction CX DX SP BP SI DI Figure 11(b): Immediate addressing mode after execution. 3. Direct Addressing Mode Direct addressing differs from immediate addressing in that the locations following the instruction opecode hold an effected memory address (EA) instead of data. This effective address is a 16-bit offset of the storage location of the operand from the current value in the data segment (DS) register. EA is combined with the contents of DS in the BIU to produce the physical address for its source operand is MOV CX, BETA This stands for move the contents of the memory location which is offset by BETA from the current value in DS into internal register CX. See Figure 12(a, b). Notice that the value assigned to constant BETA is 1234 H. PA = H H = H

40 40 4. Register Indirect Addressing Mode Register indirect addressing is similar to direct addressing in that an effective address is combined with the contents of DS to obtain a physical address. However, it differs in the way the offset is specified. This time EA resides in either a pointer register or index register within the The pointer register can be either BX or BP and the index register can be SI or DI. MOV AX, [SI] This instruction moves the contents of the memory location offset by the value of EA in SI from the current value in DS to the AX register. See Figure 13(a, b). SI contains 1234 H and DS contains 0200 H. PA = H H = H 8086 MPU XX XX IP CS DS SS ES AX BX CX DX Address Memory Content B 0E XX XX XX XX Instruction MOV CX, BETA Next Instruction SP BP SI DI ED BE Source Operand

41 Figure 12(a): Direct Addressing mode before execution MPU IP CS DS SS ES Address Memory Content B 0E XX Instruction MOV CX, BETA Next Instruction 41 AX BE ED BX CX XX XX Source Operand DX SP BP SI ED BE DI Figure 12(b): Direct Addressing mode after execution.

42 MPU Address Memory Content Instruction IP CS B 04 MOV AX, [SI] 0200 DS SS XX Next Instruction ES XX XX AX BX XX XX CX 1234 DX SP BP SI ED BE Source Operand DI Figure 13(a): Register Indirect Addressing before execution MPU IP CS DS SS ES Address Memory Content Instruction BE 1234 ED AX BX CX DX SP BP SI DI

43 B 04 MOV AX, [SI] XX Next Instruction XX XX ED BE Source Operand Figure 13(b): Register Indirect Addressing mode after execution. 5. Based Addressing Mode In the based addressing mode, the physical address of the operand is obtained by adding a direct or indirect displacement to the contents of either BX or BP and the current value in DS and SS, respectively. A MOV instruction that uses based addressing to specify the location of its destination operand is as follows: MOV [BX].BETA, AL As shown in Figure 14(a,b) the fetch and execution of this instruction causes the BIU to calculate the physical address of the destination operand from the contents of DS, BX, and the direct displacement. The result is

44 44 = H PA = H H H 6. Indexed Addressing Mode Indexed addressing works identically to the based addressing, it uses the contents of one of the index registers, instead of BX or BP, in the generation of the physical address, here is an example: MOV AL, ARRAY[SI] The example in Figure 15(a,b) shows the result of executing the MOV instruction. First the physical address for the source operand is calculated from DS, SI, and the direct displacement. PA = H H H = H Then the byte of data stored at this location, which is BEH is read into lower byte AL of the accumulator register.

45 MPU Address Memory Content Instruction IP CS DS SS ES XX MOV [BX].BETA, AL Next Instruction BEED 1000 AX BX CX XX XX DX SP BP XX XX Source Operand SI DI Figure 14(a): Based Addressing before execution MPU IP CS DS SS ES Address Memory Content XX Instruction MOV [BX].BETA, AL Next Instruction BE DE AX BX CX DX SP BP SI DI XX XX ED XX

46 Figure 14(b): Based Addressing mode after execution MPU IP CS DS SS ES Address Memory Content A XX Instruction MOV AL, ARRAY[SI] Next Instruction 46 XX XX AX BX CX XX XX DX 2000 SP BP SI DI Figure 15(a): Direct Indexed Addressing before execution MPU IP CS DS SS ES BE Address Memory Content A XX Source Operand Instruction MOV AL, ARRAY[SI] Next Instruction XX BE AX BX CX DX XX XX BE Source Operand

47 47 Figure 15(b): Direct Indexed Addressing mode after execution. 7. Based Indexed Addressing Mode Combining the based addressing mode and the indexed addressing mode together results in a new, more powerful mode known as based indexed addressing. Let us consider an example of a MOV instruction using this type of addressing. MOV AH, [BX].BETA[SI] An example of executing this instruction is illustrated in Figure 16(a,b). The address of the source operand is calculated as PA = H H H H = H Execution of this instruction causes the Value stored at this location to be written into AH. 8. String Addressing Mode The string instructions of the 8086's instruction set automatically use the source and destination index registers to specify the effective addresses of the source and destination operands, respectively. The move string instruction MOVS is an example. Notice that neither SI nor DI appears in the string instruction, but both are used during its execution.

48 MPU Address Memory Content Instruction IP CS DS SS ES A XX MOV AL, [BX].BETA[SI] Next instruction XX XX AX BX CX XX XX DX SP BP BE Source Operand 2000 SI DI Figure 16(a): Based Indexed Addressing before execution.

49 MPU Address Memory Content Instruction IP CS DS SS ES A XX MOV AL, [BX].BETA[SI] Next Instruction BE 00 AX BX CX XX XX DX SP 2000 BP SI BE Source Operand DI Figure 15(b): Based Indexed Addressing mode after execution. 9. Port Addressing Mode Port addressing is used in conjunction with the IN and OUT instructions to access input and output ports. Any of the memory addressing modes can be used for the port address for memory mapped ports. For ports in the I/O address space, only the Direct addressing mode and an Indirect addressing mode using DX are available. For example, Direct addressing of an input port is used in the instruction IN AL, 15 H This stands for input the data from the byte wide input port at address 15 H of the I/O address space to register AL. Next, let us consider another example. Using Indirect port addressing for the source operand in an IN instruction, we get:

50 50 IN AL, DX It means input the data from the byte wide input port whose address is specified by the contents of register DX. For instance, if DX equals 1234 H the contents of the port at this I/O address are loaded into AL. Problems: 1. Which register holds a count for some instruction? 2. What is the purpose of the IP register? 3. The carry flag bit is set by which arithmetic operation? 4. A number that contain 3 one bit said to have parity? 5. Find the memory address of the next instruction execute by the micro processor for the following CS:IP combinations: a. CS=1000 H and IP=2000 H b. CS=2000 H and IP=1000 H 6. Which register or registers are used as an offset address for string instruction destination in the microprocessor? 7. The stack memory is addressed by a combination of the segment plus offset. 8. Which registers of the 8086 are used in memory segmentation? 9. Categorize each flag bit of the 8086 as either a control flag or as a flag to monitor the effect of instruction execution.

51 Identify the three part of an assembly language instruction in each of the following statement: AGAIN: ADD AX, CX; ADD THE REGISTERS MOV BX, AX; SAVE RESULT 11. Identify the source and destination operand for each of the statements in 10. Instructions set 8086 has 117 instructions, these instructions divided into 6 groups: 1. Data transfer instructions 2. Arithmetic instructions 3. Logic instructions 4. Shift instructions 5. Rotate instructions 6. Advance instructions

52 52 1. Data Transfer Instructions The microprocessor has a group of data transfer instructions that are provided to move data either between its internal registers or between an internal register and a storage location in memory. Some of these instructions are: MOV use to transfer a byte or a word of data from a source operand to a destination operand. These operands can be internal registers and storage locations in memory. Notice that the MOV instruction cannot transfer data directly between a source and a destination that both reside in external memory. For instance, flag bits within the microprocessors are not modified by execution of a MOV instruction. EXAMPLES: 1. MOV DX, CS DX=CS=0100 H where DX=0100 H 2. MOV SUM, AX DS=0200 H SUM=1212 H PA=02000 H H =03212 H AL Memory location H AH Memory location H 3. If DS contain 1234 H what is the effect of executing the instruction MOV CX,[0ABCD H ] CL loaded with the content of Memory location 1234 H + ABCD H = 1CF0D H And CH is loaded with the content of Memory location 1234 H + ABCD H +1 = 1CF0E H

53 53 XCHG: in MOV instruction the original contents of the source location are preserved and the original contents of the destination are destroyed. But XCHG instruction can be used to swap data between two general purpose register or between a general purpose register and storage location in memory. EXAMPLES: 1. XCHG AX, DX (AX) (DX) 2. XCHG SUM, BX (DS (0) + SUM) BX DS=02000 H H =03234 H (3234) (BL) (3235) (BH) 2. Arithmetic Instructions Arithmetic instructions includes instructions for the addition, subtractions can be performed on numbers expressed in a variety of numeric data formats. The status that results from the execution of an arithmetic instruction is recoded in the flags of the microprocessor. The flags that are affected by arithmetic instructions are CF, AF, SF, ZF, and PF. Addition: ADD, ADC, and INC - ADD AX,BX AX= AX+BX EXAMPLE: AX= 1100 H, BX=0ABC H ADD AX, BX 1100 H + 0ABC H = 1BBC H = AX

54 - ADC AX, BX AX=AX+BX+CF 54 - INC AH AH= AH +1 EXAMPLE: The original contents of AX, BL, memory location SUM, and CF are AX=1234 H, BL= AB H, Sum=00CD H and CF=0 respectively, describe the result of execution the following sequence of instruction: ADD AX, SUM ADC BL, 05 H INC SUM 1. AX= 1234 H + 00CD H = 4301 H CF=0 2. BL= AB H +05 H +0=B0 H CF=0 3. SUM=00CD H + 1=00CE H CF=0 Instructions AX BL SUM CF Initial state ADD AX, SUM ADC BL, 05 H INC SUM 1234 H 4301 H 4301 H 4301 H AB H AB H B0 H B0 H 00CD H 00CD H 00CD H 00CE H Subtraction: SUB, SBB, DEC, and NEG - SUB AX, BX AX=AX BX

55 - SBB AX, BX AX= AX - BX CF 55 EXAMPLE: BX=1234 H, CX=0123 H, CF=0 SBB BX, CX BX=1234 H H -0 =1111 H - DEC subtract 1 from its operand - NEG BX (2's complement) 00 H BX 's complement of BX BX= 3A H NEG BX H +FFC6 H C 6 Multiplication and Division MUL, DIV - MUL CL (AX)= AL* CL - MUL CX (DX, AX) = AX * CX - DIV CL (AH), (AL) = AX/CL And AL the quotient Where AH is the reminder EXAMP LE:

56 - DIV CX DX, AX= (DX,AX)/CX AX contain the Quotient DX contain the reminder 56 EXAMPLE: MUL CL where AL=-1 CL= -2 AX= FF H * FE H = FD02 H 3. Logical Instructions (AND, OR, XOR, NOT) Instructions MOV AL, B AND AL, B OR AL, B XOR AL, B NOT AL AL B B B B B 4. Shift Instructions The four types of shift instructions can perform two basic types of shift operations. They are the logical shift and arithmetic shift. Each of these operations can be performed to the right or to the left. Instructions Meaning format Operation Flags affected

57 57 SAL/SHL Shift arithmetic left/shift logical left SAL/SHL D, Count Shift the D left by the number of bit positions equal to count and fill the vacated bits positions on the right with zeros OF, CF SHR Shift logical right SAR SHL CF Shift arithmetic right SHR D, Count SAR D, Count Shift the D right by the number of bit position equal to count and fill the vacated bit positions on the left with zeros Shift the D right by the number of bit positions equal to count and fill the vacated bit positions on the left with the original most significant bit 0 OF, CF OF,SF, ZF, AF, PF, CF SAL CF SHR 0 0 CF

58 SAR CF Rotate Instructions ROL (Rotate Left) CF ROR (Rotate Right) CF RCL (Rotate Carry Left) CF RCR (Rotate Carry Right) CF

59 59 6. Advance instruction (Program and Control Instruction) In this section many of instructions that can be executed by the 8086 microprocessor are described, furthermore, these instructions use to write simple programs. The following topics are discussed in this section: 1. Flag control instructions 2. Compare instruction 3. Jump instructions 4. String instruction 1. Flag Control Instruction The 8086 microprocessor has a set of flags which either monitor the status of executing instruction or control options available in its operation. The instruction set includes a group of instructions which when execute directly affect the setting of the flags. The instructions are: LAHF: load AH from flags SAHF: store AH into flags CLC: clear carry, CF=0 STC: set carry, CF=1 CMC: complement carry, CF= CF CLI: clear interrupt, IF=0 STI: set interrupt, IF=1

60 EXAMPLE: 60 Write an instruction to save the current content of the flags in memory location MEM1 and then reload the flags with the contents of memory location MEM2 Solution: LAHF MOV MEM1, AH MOV AH, MEM2 SAHF 2. Compare Instruction There is an instruction included instruction set which can be used to compare two 8-bit number or 16-bit numbers. It is the compare (CMP) instruction. The operands can reside in a storage location in memory, a register within the MPU. Instruction Meaning Format Operation Flag affected CMP Compare CMP D,S D-S CF,AF,OF,PF,SF, Destination Register Register Memory Register Memory Accumulator Source Register Memory Register Immediate Immediate Immediate The process of comparison performed by the CMP instruction is basically a subtraction operation. The source operand is subtracted from the destination operand. However the result of this subtraction

61 61 is not saved. Instead, based on the result the appropriate flags are set or reset. EXAMPLE: lets the destination operand equals and that the source operand equals Subtraction the source from the destination, we get _ Replacing the destination operand with its 2's complement and adding No carry is generated from bit 3 to bit 4, therefore, the auxiliary carry flag AF is at logic There is a carry out from bit 7. Thus carry flag CF is set. 3. Even through a carry out of bit 7 is generated; there is no carry from bit 6 to bit 7. This is an overflow condition and the OF flag is set. 4. There are an even number of 1s, therefore, this makes parity flag PF equal to Bit 7 is zero and therefore sign flag SF is at logic 0.

62 62 6. The result that is produced is nonzero, which makes zero flag ZF logic JUMP Instruction The purpose of a jump instruction is to alter the execution path of instructions in the program. The code segment register and instruction pointer keep track of the next instruction to be executed. Thus a jump instruction involves altering the contents of these registers. In this way, execution continues at an address other than that of the next sequential instruction. That is, a jump occurs to another part of the program. There two type of jump instructions: a. Unconditional jump. b. Conditional jump. In an unconditional jump, no status requirements are imposed for the jump to occur. That is, as the instruction is executed, the jump always takes place to change the execution sequence. See Figure 16 Instruction Meaning Format Operation Flags affected JMP Unconditional jump JMP operand Jump is to the address specified by operand None

63 63 Part I JMP AA Part II UnconditionalJumpinstruction Locations skipped due to jump AA XXX Nextinstructionexecuted PART III Figure 16: Unconditional jump program sequence. On the other hand, for a conditional jump instruction, status conditions that exist at the moment the jump instruction is executed decide whether or not the jump will occur. If this condition or conditions are met, the jump takes place, otherwise execution continues with the next sequential instruction of the program. The conditions that can be referenced by a conditional jump instruction are status flags such as carry (CF), parity (PF), and overflow (OF). See Figure 17 Instruction Meaning Format Operation Flags affected JCC Conditional jump Jcc operand If the specific condition cc is true, the jump to the address specified by the operand is initiated, otherwise the next instruction is executed None The following table lists some of the conditional jump instructions:

64 64 Instruction JAE/JNB JB/JNAE JC JCXZ JE/JZ JNC JNE/JNZ JNO JNP/JPO JNS JO JP/JPE JS Meaning Jump if above or equal jump if not below Jump if below/jump if not above or equal Jump if carry Jump if CX is zero Jump if equal/jump if zero Jump if not carry Jump if not equal/ jump if not zero Jump if not overflow Jump if parity/jump if parity odd Jump if not sign Jump if overflow Jump if parity/jump if parity Even Jump if sign Part I JCC AA XXXXX Part II Conditional Jump instruction next instruction executed if condition not met Locations skipped if jump taken AA XXX PART III Figure 17: Conditional jump program sequence.